1. Field of the Invention
Embodiments of the present disclosure are directed to non-volatile memory technology.
2. Description of the Related Art
Semiconductor memory devices have become more popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrical Erasable Programmable Read Only Memory (EEPROM), including flash EEPROM, and Electronically Programmable Read Only Memory (EPROM) are among the most popular non-volatile semiconductor memories.
One example of a flash memory system uses the NAND structure, which includes arranging multiple transistors in series between two select gates. The transistors in series and the select gates are referred to as a NAND string. FIG. 1 is a top view showing one NAND string 30. FIG. 2 is an equivalent circuit thereof. The NAND string depicted in FIGS. 1 and 2 includes four transistors 10, 12, 14 and 16 in series between a first select gate 12 and a second select gate 22. Select gate 12 connects the NAND string to bit line 26. Select gate 22 connects the NAND string to source line 28. Select gate 12 is controlled by applying appropriate voltages to control gate 20CG via selection line SGD. Select gate 22 is controlled by applying the appropriate voltages to control gate 22CG via selection line SGS. Each of the transistors 10, 12, 14 and 16 includes a control gate and a floating gate, forming the gate elements of a memory cell. For example, transistor 10 includes control gate 10CG and floating gate 10FG. Transistor 12 includes control gate 12CG and a floating gate 12FG. Transistor 14 includes control gate 14CG and floating gate 14FG. Transistor 16 includes a control gate 16CG and a floating gate 16FG. Control gate 10CG is connected to word line WL3, control gate 12CG is connected to word line WL2, control gate 14CG is connected to word line WL1, and control gate 16CG is connected to word line WL0. Another type of memory cell useful in flash EEPROM systems utilizes a non-conductive dielectric material in place of a conductive floating gate to store charge in a non-volatile manner.
Note that although FIGS. 1 and 2 show four memory cells in the NAND string, the use of four transistors is only provided as an example. A NAND string can have less than four memory cells or more than four memory cells. For example, some NAND strings will include eight memory cells, 16 memory cells, 32 memory cells, etc. The discussion herein is not limited to any particular number of memory cells in a NAND string. Relevant examples of NAND-type flash memories and their operation are provided in the following U.S. patents/patent applications, all of which are incorporated herein by reference in their entirety: U.S. Pat. Nos. 5,570,315; 5,774,397; 6,046,935; 5,386,422; 6,456,528; and U.S. patent application Ser. No. 09/893,277 (Publication No. US2003/0002348). Other types of non-volatile memory in addition to NAND flash memory can also be used in accordance with embodiments.
A typical architecture for a flash memory system using a NAND structure will include several NAND strings. For example, FIG. 3 shows three NAND strings 40, 42 and 44 of a memory array having many more NAND strings. Each of the NAND strings of FIG. 3 includes two select transistors or gates and four memory cells. For example, NAND string 40 includes select transistors 50 and 60, and memory cells 52, 54, 56 and 58. NAND string 42 includes select transistors 70 and 80, and memory cells 72, 74, 76 and 78. Each string is connected to the source line by a select gate 60, 80, etc. A selection line SGS is used to control the source side select gates. The various NAND strings are connected to respective bit lines by select gates 50, 70, etc., which are controlled by select line SGD. In other embodiments, the select lines do not necessarily need to be in common. Word line WL3 is connected to the control gates for memory cell 52 and memory cell 72. Word line WL2 is connected to the control gates for memory cell 54 and memory cell 74. Word line WL1 is connected to the control gates for memory cell 56 and memory cell 76. Word line WL0 is connected to the control gates for memory cell 58 and memory cell 78. As can be seen, a bit line and respective NAND string comprise a column of the array of memory cells. The word lines comprise the rows of the array. Each word line connects the control gates of each memory cell in the row. For example, word line WL2 is connected to the control gates for memory cells 54, 74 and 94. In many implementations, the word lines form the control gate of each memory cell in the row.
FIG. 4 illustrates an exemplary array 100 of NAND strings, such as those shown in FIGS. 1-3. Along each column, a bit line 26 is coupled to a drain terminal of the bit line select gate for the NAND string. Along each row of NAND strings, a source line 28 may connect all the source terminals of the source line select gates of the NAND strings.
The array 100 of memory cells is divided into a large number of blocks of memory cells. As is common for flash EEPROM systems, the block is the unit of erase and may be referred to as an erase block or physical block. Each block can contain the minimum number of memory cells that are erased together, although multiple blocks may be erased simultaneously. Smaller units of cells may be erased together in some implementations. In FIG. 4, a block includes the cells connected to a common set of word lines WL0-WL3. For example, block 90 includes NAND strings 40 and 42 and each other string 30 connected to word lines WL0-WL3.
When programming an EEPROM or flash memory device, typically a program voltage is applied to the control gate and the bit line is grounded. Electrons from the channel are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory cell is raised so that the memory cell is in a programmed state. The floating gate charge and threshold voltage of the cell can be indicative of a particular state corresponding to stored data (analog or digital). More information about programming can be found in U.S. patent application Ser. No. 10/379,608, titled “Self Boosting Technique,” filed on Mar. 5, 2003; and in U.S. patent application Ser. No. 10/629,068, titled “Detecting Over Programmed Memory,” filed on Jul. 29, 2003, both applications are incorporated herein by reference in their entirety.
In order to erase memory cells of a NAND type flash memory, electrons are transferred from the floating gate of each memory cell to the well region and substrate. Typically, one or more high voltage erase pulses are applied to the well region to attract electrons away from the floating gate of each memory cell to the well region. The word lines of each memory cell are grounded or supplied with 0V to create a high potential across the tunnel oxide region to attract the electrons. If each memory cell of a NAND string is not erased after application of an erase voltage pulse, the size of the pulse can be increased and reapplied to the NAND string until each memory cell is erased.
It is common for individual memory cells to erase at different rates and to different threshold voltage levels during erase operations. Slight variations in device dimensions, spacing and/or material compositions for instance, will influence the behavior of individual memory cells within a block or string of memory cells. Consequently, some memory cells will undergo a larger or smaller shift in threshold voltage when subjected to an erase voltage as compared to other memory cells. Moreover, groupings of memory cells such as a NAND string are often verified for an erased state or condition simultaneously. If any memory cell of the string is not erased as detected by a verify operation, the entire NAND string is enabled for erasing during application of an additional erase voltage pulse. This can result in faster erasing cells being placed into a deeper erased state than desired. The range or distribution of threshold voltages for a group of erased cells is increased by such factors.
A technique generally referred to as soft programming has been used to adjust the threshold voltages of one or more memory cells during erase operations. Soft programming can tighten or narrow the distribution of threshold voltages for a group of memory cells after being erased. Soft programming typically attempts to shift the threshold voltage of one or more memory cells closer to the verify level used during erasing. Soft programming includes applying a relatively low program voltage—lower than that used for actual programming—to one or more memory cells. Typically a program voltage is applied as a series of pulses that are increased between each application. Like erase operations, soft programming is often carried out at the block level by applying the soft programming voltage pulses to every word line of a block of memory cells. For example, soft programming voltage pulses may be applied to word lines WL0, WL1, WL2, and WL3 of block 90 to soft program each cell of block 90. Individual NAND strings are verified for a soft programmed condition after application of one or more soft programming pulses. If a NAND string is determined to be soft programmed, it is necessary to inhibit it from soft programming during subsequent applications of the soft programming voltage to continue soft programming other NAND strings sharing the common set of word lines. For example, it may be necessary to inhibit memory cells 72, 74, 76, and 78 of NAND string 42 from being soft programmed, while continuing to apply soft programming pulses to soft program memory cells 52, 54, 56, and 58 of NAND string 40.
Traditionally, soft programming is inhibited in a particular NAND string by raising the bit line voltage for the string. After raising the bit line voltage, the NAND string is electrically disconnected from the bit line by turning off the drain select gate. Because the NAND string is electrically disconnected from the bit line, the soft programming voltage applied to the word lines will cause the channel region of the inhibited NAND string to be boosted to a positive voltage level due to capacitive charge coupling. The positive voltage level of the NAND string eliminates the large voltage potential necessary to inject electrons into the floating gate regions of the memory cells, and thus, inhibits soft programming.
If the boosting is not sufficient in a NAND string to be inhibited from soft programming, the memory cells of the string may inadvertently be soft programmed. For example, when applying the soft programming voltage to word lines WL0, WL1, WL2, and WL3 to soft program NAND string 40 while inhibiting NAND string 42, one of the memory cells 72, 74, 76, or 80 of NAND string 42 may inadvertently be soft programmed. This type of inadvertent soft programming is often referred to as soft programming disturb.